1. Field of the Invention
The present invention relates generally to integrated circuit memory devices, and more specifically to a circuit and method for preventing incorrect writing of data in a dual port cache tag memory which utilizes a snoop valid bit.
2. Description of the Prior Art
One type of memory used in computer systems is a cache memory. This is a relatively small, fast memory which resides in the system between the central processor and main system memory. Cache memories include data memory fields for storing data cached from system memory, and tag memory fields for storing the addresses corresponding to the data stored in the data cache.
Some cache tag memory devices, such as that described in the application entitled DUAL-PORT CACHE TAG MEMORY, cited above, have two ports which can access a memory array asynchronously. In devices designed specifically for use as cache tag memories, one of the data ports can write data to a single bit of an entry in the array. This bit is known in the art as a "snoop valid bit", and is used to indicate that the contents of a local processor cache memory have been invalidated by processing occurring elsewhere in the computer system. When another processor or other device in the system writes data to a memory location stored in a local processor cache, that entry is no longer current. The entry is therefore marked invalid by resetting the snoop valid bit for that entry to zero.
In designs such as used by the above-cited application, the snoop valid bit for an entry can be reset to 0 only by the port which snoops the main memory bus, and once reset cannot be set to a value of 1 again until that entry is later reloaded with a new value. Thus, invalidation of an entry is an irreversible act. If invalidation occurs incorrectly, valid cache entries will be marked as invalid, causing a cache miss the next time such entries are referenced.
When cache tag memory chips are connected to provide wider entries as described in the cited application, a signal indicating a match must be communicated between the chips. If this signal is delayed in reaching the snoop bit invalidation circuitry due to parasitic capacitances, the snoop valid bit could be erroneously reset to 0.
It would therefore be desirable to provide a control circuit for dual port cache tag memories which ensures that a snoop valid bit is not erroneously reset to 0. It would be further desirable for such a control circuit to be simple to construct, and not add complexity to a memory cycle for the memory.